/**********************************************************************
 Copyright (c) 2006-2009 MStar Semiconductor, Inc.
 All rights reserved.

 Unless otherwise stipulated in writing, any and all information contained
 herein regardless in any format shall remain the sole proprietary of
 MStar Semiconductor Inc. and be kept in strict confidence
 (MStar Confidential Information) by the recipient.
 Any unauthorized act including without limitation unauthorized disclosure,
 copying, use, reproduction, sale, distribution, modification, disassembling,
 reverse engineering and compiling of the contents of MStar Confidential
 Information is unlawful and strictly prohibited. MStar hereby reserves the
 rights to any and all damages, losses, costs and expenses resulting therefrom.

* File  : Board.h
**********************************************************************/
#include "drvXC_IOPort.h"

//#include "MSD804KRTM.h"
#include "MSD8832RKM2.h"

#include "mapi_types.h"
#include "mapi_syscfg_table.h"
#include "mapi_gpio_devTable.h"
#include "mapi_i2c_devTable.h"
#include "mapi_video.h"
#include "drvAUDIO_if.h"
#include "apiDMX.h"

#include "SN_MMAP.h"
#include "VGA_EDID.h"
#include "HDMI_EDID.h"
#include "mapi_vd.h"
#include "../audioamp/device_audio_amp_MSH9010.h"

#define BOARD_DEFINE_ENABLE         0x01

#define BOARD_COMMON_NULL           0x00

// Board Name
#define BOARD_NAME                  "MST065B_ATSC"

// software version
#define SOFTWARE_VERSION            "0001"
//**********************************************************************
//** System-TvParam
//**********************************************************************
#define BOARD_TV_PRODUCT_TYPE       E_ATV_Plus_DTV
#define BOARD_ATV_SYSTEM_TYPE       E_NTSC_ENABLE

//For Example:(DVBT_ENABLE|DVBC_ENABLE|DVBS_ENABLE |DVBT2_ENABLE|DVBS2_ENABLE|DTMB_ENABLE|ATSC_ENABLE|ISDB_ENABLE)
#define BOARD_DTV_TYPE              ATSC_ENABLE
#define BOARD_AUDIO_SYSTEM_TYPE     E_BTSC_ENABLE
#define BOARD_STB_SYSTEM_TYPE       E_STB_DISABLE

//For Example:(_FBL_ENABLE|_PWS_ENABLE| _AUDIO_SIF_ENABLE | _PRE_SCALE_DOWN_ENABLE | _CCIR_VEOUT_ENABLE | _SCART_OUT_ENABLE | _MM_FRC_ENABLE | _MARCOVISION_ENABLE )
#define BOARD_IP_ENABLE             _SCART_OUT_ENABLE
#define BOARD_ROUTE_PATH_1          E_ROUTE_ATSC
#define BOARD_ROUTE_PATH_2          BOARD_COMMON_NULL
#define BOARD_ROUTE_PATH_3          BOARD_COMMON_NULL
#define BOARD_ROUTE_PATH_4          BOARD_COMMON_NULL

#define BOARD_SAW_TYPE SILICON_TUNER
#define BOARD_SAR_CHANNEL E_SAR_NC

static S_TV_TYPE_INFO BOARD_TV_PARAM=
{
    BOARD_TV_PRODUCT_TYPE,
    BOARD_ATV_SYSTEM_TYPE,
    BOARD_DTV_TYPE,
    BOARD_AUDIO_SYSTEM_TYPE,
    BOARD_STB_SYSTEM_TYPE,
    BOARD_IP_ENABLE,
    {
        BOARD_ROUTE_PATH_1,
        BOARD_ROUTE_PATH_2,
        BOARD_ROUTE_PATH_3,
        BOARD_ROUTE_PATH_4,
    }

};

//**********************************************************************
//** Video relative setting
//**********************************************************************

//EN_Mode_1135,
//EN_Mode_1135_1P5
#define BOARD_VD_CAP_WIN_MODE           EN_Mode_Dynamic

//**********************************************************************
//** Panel relative setting
//**********************************************************************

#define BOARD_PWM_PORT                  2
#define BOARD_LVDS_CONNECT_TYPE         0x00
#define PANEL_PDP_10BIT                 1
#define PANEL_SWAP_LVDS_POL             1
#define PANEL_SWAP_LVDS_CH              0
#define PANEL_CONNECTOR_SWAP_PORT       0
#define LVDS_PN_SWAP_L                  0x00
#define LVDS_PN_SWAP_H                  0x00

//**********************************************************************
//** System-I2C
//**********************************************************************

//Bus Info Define
#define BOARD_I2C_SWBUS_NUM             3
#define BOARD_I2C_HWBUS_NUM             0
#define BOARD_I2C_DEVICE_NUM            5

//Bus Define
static SWI2CBus_t BOARD_I2C_SWBUS[BOARD_I2C_SWBUS_NUM]=
{
    //Example for SW I2C => { 1, PAD_DDCR_CK, PAD_DDCR_DA, 60, }, //SW_I2C  /SCL_PAD /SDA_PAD /Delay
    //Bus-0
    {PAD_DDCR_CK, PAD_DDCR_DA,60}, //EEPROM
    //Bus-1
    {PAD_TGPIO2, PAD_TGPIO3,60}, //TUNER
    //Bus-2
    {PAD_I2S_IN_BCK, PAD_I2S_IN_SD, 60}, //EDINBURGH
    //Bus-3
    //{PAD_DDCDB_CK, PAD_DDCDB_DA, 60}, //HDMI 1 DDC
    //Bus-4
    //{PAD_DDCDC_CK, PAD_DDCDC_DA, 60}, //HDMI 1 DDC
    //Bus-5
    //{PAD_DDCDD_CK, PAD_DDCDD_DA, 60}, //HDMI 1 DDC


};

static HWI2CBus_t BOARD_I2C_HWBUS[BOARD_I2C_HWBUS_NUM];



//Device Info Define
static I2CDeviceInfo_s  Board_I2C_Dev[BOARD_I2C_DEVICE_NUM] = {
    //Example => { TUNER1, 1, 0xC2 }, //gID(U32)  /i2c_bus(U8) /slave_id(U8)
    { EEPROM, 0, 0xA4 }, //gID(U32)  /i2c_bus(U8) /slave_id(U8)
    //{ EEPROM2, 0, 0xA8 }, //gID(U32)  /i2c_bus(U8) /slave_id(U8)
    {TUNER1, 1, 0xC0 }, //gID(U32)  /i2c_bus(U8) /slave_id(U8)
    {DEMOD_DYNAMIC_SLAVE_ID_1, 2, 0xF2},
    {DEMOD_DYNAMIC_SLAVE_ID_2, 2, 0xA2},
    //{EDID_D0, 3, 0xA0},
    //{EDID_D1, 4, 0xA0},
    //{EDID_D2, 5, 0xA0},
    {MEMC_MST7420A, 0, 0x40 }, //gID(U32)  /i2c_bus(U8) /slave_id(U8)  Ursa7
};


//**********************************************************************
//** System-GPIO
//**********************************************************************
#define BOARD_GPIO_NUM                  5

static GPIOInfo_t  Board_GPIO_Setting[BOARD_GPIO_NUM] =
{
    //Example => { MUTE, 0, PAD_GPIO_PM1 }, //gID(U32)  /gInvertor(U8) /gPadNo(U32)


    { INV_CTL, 0, PAD_GPIO_PM5 }, //gID(U32)  /gInvertor(U8) /gPadNo(U32) ok
    { PANEL_CTL, 0, PAD_GPIO_PM1 }, //gID(U32)  /gInvertor(U8) /gPadNo(U32) ok
    { Audio_Amplifier, 1, PAD_PWM1 },//gID(U32)  /gInvertor(U8) /gPadNo(U32) ok
    //{ PCM_POWER_CTRL, 0, PAD_PWM0 },//gID(U32)  /gInvertor(U8) /gPadNo(U32)  ok
    //{ SPI_WP, 1, PAD_GPIO_PM0 },//gID(U32)  /gInvertor(U8) /gPadNo(U32)  ok
    {Demodulator_Reset, 0, PAD_I2S_IN_WS},
    { HDMI_5VPWR_A, 0, PAD_SAR2 }, //input, HDMI_5VPWR_A
};
//**********************************************************************
//** System-IR
//**********************************************************************

#define BOARD_IR_CRYSTAL_CLK_HZ         12000000

static PM_IrRegCfg_t  Board_IR_Setting =
{
    1,                      /// IR mode selection
    0xBF,                   /// IR enable control
    0x01,                   /// IR enable control 1
    0x80,                   /// IR header code 0
    0x7F,                   /// IR header code 1
    140000,                 /// IR timerout counter
    2,                      /// Customer codes: 1 or 2 bytes
    32,                     /// Code bits: 0x00~0x7F

    //Time, upper bound, low bound
    {9000,20,(-20)},        // header code time
    {4500,20,(-20)},        //off code time
    {2500,20,(-20)},        /// off code repeat time
    {560,35,(-30)},         /// logical 0/1 high time
    {1120,20,(-20)},        /// logical 0 time
    {2240,20,(-20)},        /// logical 1 time

};

#define Board_PowerUpKeyCode 0x00

//**********************************************************************
//** InputMux
//**********************************************************************

#define BOARD_Demodulator               1       //1: internal, 0:external
#define BOARD_ATV_InputSrc_Type         E_MAPI_INPUT_SOURCE_INVALID

#define BOARD_Scart_1_FAST_BLACKING_Ping16  3   //0:SCART_FB_NONE, 1:SCART_FB0, 2:SCART_FB1, 3:SCART_FB2, 4:
#define BOARD_Scart_2_FAST_BLACKING_Ping16  0   //0:SCART_FB_NONE, 1:SCART_FB0, 2:SCART_FB1, 3:SCART_FB2, 4:
#define BOARD_Scart_OUT_MODE                3   // 0: SCART1:TV, SCART2:MONITOR          //SCART_OUT_TV_MONITOR
                                                                                    // 1: SCART1:MONITOR, SCART2:TV     //SCART_OUT_MONITOR_TV
                                                                                    // 2: SCART1:TV, SCART2:NONE
                                                                                    // 3: SCART1:MONITOR, SCART2:NONE  //SCART_OUT_MONITOR_NONE
#define BOARD_Scart_1_AUTO_SCART_Ping8 2      //0: INT_PIN8_HSYNC0, 1:INT_PIN8_HSYNC1, 2:INT_PIN8_HSYNC2, 3:INT_PIN8_NONE
#define BOARD_Scart_2_AUTO_SCART_Ping8  3       //0: INT_PIN8_HSYNC0, 1:INT_PIN8_HSYNC1, 2:INT_PIN8_HSYNC2, 3:INT_PIN8_NONE

ATVExtDemodInfo_t   BOARD_ExtDemodInfo =
{
    BOARD_Demodulator,
    BOARD_ATV_InputSrc_Type
};

#define SCART_ID_LEVEL_0V           0  ///< Scart Pin8 ADC input digital value setting
//#define SCART_ID_LEVEL_1V         0
//#define SCART_ID_LEVEL_2V         0
#define SCART_ID_LEVEL_3V          7  ///<Scart voltage 3V = 7(ADC regiater value)
#define SCART_ID_LEVEL_4V         14  ///<Scart voltage 4V = 10(ADC regiater value)
//#define SCART_ID_LEVEL_4p5V       35
#define SCART_ID_LEVEL_5V         12  ///<Scart voltage 5V = 12(ADC regiater value)
#define SCART_ID_LEVEL_6V         15  ///<Scart voltage 6V = 15(ADC regiater value)
//#define SCART_ID_LEVEL_7V         35
//#define SCART_ID_LEVEL_8V           45//60
#define SCART_ID_LEVEL_9V         23  ///<Scart voltage 9V = 23(ADC regiater value)
//#define SCART_ID_LEVEL_9p5V       60
#define SCART_ID_LEVEL_10V        120  ///<Scart voltage 10V = 26(ADC regiater value)

#define BOARD_SCART_LEVEL_4_3 SCART_ID_LEVEL_10V
#define BOARD_SCART_LEVEL_16_9 SCART_ID_LEVEL_4V
#define BOARD_SCART_LEVEL_NONE  SCART_ID_LEVEL_0V
ScartInfo_t BOARD_ScarInfo  =
{
    BOARD_Scart_1_FAST_BLACKING_Ping16,
    BOARD_Scart_2_FAST_BLACKING_Ping16,
    BOARD_Scart_OUT_MODE,
    BOARD_Scart_1_AUTO_SCART_Ping8,
    BOARD_Scart_2_AUTO_SCART_Ping8,
    BOARD_SCART_LEVEL_16_9,
    BOARD_SCART_LEVEL_4_3,
    BOARD_SCART_LEVEL_NONE,
};

// DVBT
/*
MS_U8 u8BOARD_DVBT_DSPRegInitExt[]={
                                                                1, // version, should be matched with library
                                                                0, // reserved
                                                                0, // Size_L
                                                                0, // Size_H
                                                                E_DMD_DVBT_CFG_IQ_SWAP, // Addr_L
                                                                E_DMD_DVBT_CFG_IQ_SWAP>>8, // Addr_H
                                                                0xFF, // Mask
                                                                0x00}; // Value
*/
MS_U8 u8BOARD_DVBT_DSPRegInitExt[]={};
extern MS_U8 u8BOARD_DMD_DVBT_InitExtConf[SAW_NUMS][u32_BOARD_DMD_Init_Config_Length];
MS_U8* u8BOARD_DMD_DVBT_InitExt=u8BOARD_DMD_DVBT_InitExtConf[BOARD_SAW_TYPE];
MS_U8 u8BOARD_DMD_DVBT_InitExtConf[SAW_NUMS][u32_BOARD_DMD_Init_Config_Length]=
{
{// 0:DUAL_SAW
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    0, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    0, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5// u8PGAGain : default 5
},
{
// 1 EXTERNAL_SINGLE_SAW
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    0, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    0, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5// u8PGAGain : default 5
},
{
// 2 INTERNAL_SINGLE_SAW_DIF or SILICON_TUNER
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    0, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    0, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5// u8PGAGain : default 5
},
{
// 3 NO_SAW
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    0, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    0, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5// u8PGAGain : default 5
},
{
// 4 INTERNAL_SINGLE_SAW_VIF
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    1, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    1, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5// u8PGAGain : default 5
},
{
// 5 NO_SAW (DIF)
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    1, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    0, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5, // u8PGAGain : default 5
}
};
// DVBC
/*
    E_DMD_DVBC_NO_SIGNAL_GAIN_TH_L,
    E_DMD_DVBC_NO_SIGNAL_GAIN_TH_H,
*/
/*
MS_U8 u8BOARD_DVBC_DSPRegInitExt[]={
                                                                    1, // version, should be matched with library
                                                                    0, // reserved
                                                                    0, // Size_L
                                                                    0, // Size_H
                                                                    E_DMD_DVBC_OP_NORMALIF_EN, // Addr_L
                                                                    E_DMD_DVBC_OP_NORMALIF_EN>>8, // Addr_H
                                                                    0xFF, // Mask
                                                                    0x01}; // Value
*/
MS_U8 u8BOARD_DVBC_DSPRegInitExt[]={};
extern MS_U8 u8BOARD_DMD_DVBC_InitExtConf[SAW_NUMS][u32_BOARD_DMD_Init_Config_Length];
MS_U8* u8BOARD_DMD_DVBC_InitExt=u8BOARD_DMD_DVBC_InitExtConf[BOARD_SAW_TYPE];
MS_U8 u8BOARD_DMD_DVBC_InitExtConf[SAW_NUMS][u32_BOARD_DMD_Init_Config_Length]=
{
{// 0:DUAL_SAW
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    0, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    0, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5// u8PGAGain : default 5
},
{
// 1 EXTERNAL_SINGLE_SAW
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    0, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    0, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5// u8PGAGain : default 5
},
{
// 2 INTERNAL_SINGLE_SAW_DIF or SILICON_TUNER
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    0, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    0, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5// u8PGAGain : default 5
},
{
// 3 NO_SAW
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    0, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    0, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5// u8PGAGain : default 5
},
{
// 4 INTERNAL_SINGLE_SAW_VIF
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    1, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    1, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5// u8PGAGain : default 5
},
{
// 5 NO_SAW (DIF)
    3, // version
    0, // reserved
    0xFF, // TS_CLK
    1, // RFAGC tristate control default value, 1:trisate 0:non-tristate,never modify unless you know the meaning
    (MS_U8)(36167>>24), // IF Frequency
    (MS_U8)(36167>>16),
    (MS_U8)(36167>>8),
    (MS_U8)(36167>>0),
    (MS_U8)(45474>>24), // FS Frequency
    (MS_U8)(45474>>16),
    (MS_U8)(45474>>8),
    (MS_U8)(45474>>0),
    0, // IQ Swap
    1, // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
    0, // u8PadSel : 0=Normal, 1=analog pad
    0, // bPGAEnable : 0=disable, 1=enable
    5, // u8PGAGain : default 5
}
};

#define BOARD_INPUTMUX_NUM              MAPI_INPUT_SOURCE_NUM


static MAPI_VIDEO_INPUTSRCTABLE Board_Input_Mux_Table[BOARD_INPUTMUX_NUM] =
{
    //1~10
    //MAPI_INPUT_SOURCE_VGA,
    {2,         {INPUT_PORT_ANALOG0,            INPUT_PORT_ANALOG0_SYNC}},///<VGA input
    //MAPI_INPUT_SOURCE_ATV,
    {1,         {INPUT_PORT_YMUX_CVBS1,         INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_CVBS,         ///<AV 1
    {1,         {INPUT_PORT_YMUX_CVBS0,         INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_CVBS2,        ///<AV 2
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_CVBS3,        ///<AV 3
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_CVBS4,        ///<AV 4
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_CVBS5,        ///<AV 5
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_CVBS6,        ///<AV 6
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_CVBS7,        ///<AV 7
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_CVBS8,        ///<AV 8
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input

    //11~20
    //MAPI_INPUT_SOURCE_CVBS_MAX,     ///<AV max
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_SVIDEO,       ///<S-video 1
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<VGA input
    //MAPI_INPUT_SOURCE_SVIDEO2,      ///<S-video 2
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_SVIDEO3,      ///<S-video 3
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_SVIDEO4,      ///<S-video 4
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_SVIDEO_MAX,   ///<S-video max
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_YPBPR,        ///<Component 1
    {1,         {INPUT_PORT_ANALOG1,            INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_YPBPR2,       ///<Component 2
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_YPBPR3,       ///<Component 3
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_YPBPR_MAX,    ///<Component max
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input

    //21~30
    //MAPI_INPUT_SOURCE_SCART,        ///<Scart 1
    {0,         {INPUT_PORT_ANALOG2,           INPUT_PORT_YMUX_CVBS1}},  ///<TV input
    //MAPI_INPUT_SOURCE_SCART2,       ///<Scart 2
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_SCART_MAX,    ///<Scart max
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_HDMI,         ///<HDMI 1
    {1,         {INPUT_PORT_DVI3,               INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_HDMI2,        ///<HDMI 2
    {1,         {INPUT_PORT_DVI2,               INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_HDMI3,        ///<HDMI 3
    {1,         {INPUT_PORT_DVI0,               INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_HDMI4,        ///<HDMI 4
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_HDMI_MAX,     ///<HDMI max
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_DTV,          ///<DTV
    {1,         {INPUT_PORT_MVOP,               INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_DVI,          ///<DVI 1
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input


    //31~
    //MAPI_INPUT_SOURCE_DVI2,         ///<DVI 2
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_DVI3,         ///<DVI 2
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_DVI4,         ///<DVI 4
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_DVI_MAX,      ///<DVI max
    {0,         {INPUT_PORT_NONE_PORT,          INPUT_PORT_NONE_PORT}},  ///<TV input

    // Application source
    //MAPI_INPUT_SOURCE_STORAGE,  ///<Storage
    {1,         {INPUT_PORT_MVOP,               INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_KTV,      ///<KTV
    {1,         {INPUT_PORT_MVOP,               INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_JPEG,     ///<JPEG
    {1,         {INPUT_PORT_MVOP,               INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_DTV2
    {0,         {INPUT_PORT_MVOP,               INPUT_PORT_NONE_PORT}},  ///<TV input
    //MAPI_INPUT_SOURCE_STORAGE2,     ///<JPEG
    {0,         {INPUT_PORT_MVOP,               INPUT_PORT_NONE_PORT}},  ///<TV input

};



//**********************************************************************
//** WatchDog
//**********************************************************************

#define BOARD_WATCHDOG_ENABLE 			1
#define BOARD_WATCHDOG_TIMER_REG		0x00003008
#define BOARD_WATCHDOG_TIMER            10

static WDTInfo_t BOARD_WDTInfo = {MAPI_TRUE, BOARD_WATCHDOG_TIMER_REG , BOARD_WATCHDOG_TIMER};

//**********************************************************************
//** AudioInputSrcMux
//**********************************************************************

#define BOARD_AUDIO_INPUT_SOURCE_TYPE_SIZE  20
#define BOARD_AUDIO_PATH_TYPE_SIZE          8
#define BOARD_AUDIO_OUTPUT_TYPE_SIZE        6

static AudioMux_t BOARD_AudioMux_t[BOARD_AUDIO_INPUT_SOURCE_TYPE_SIZE] =
{
    {AUDIO_DSP1_DVB_INPUT},     // AUDIO_SOURCE_DTV
    {AUDIO_DSP3_DVB_INPUT},     // AUDIO_SOURCE_DTV2
    {AUDIO_DSP1_SIF_INPUT},     // AUDIO_SOURCE_ATV
    {AUDIO_AUIN2_INPUT},        // AUDIO_SOURCE_PC
    {AUDIO_AUIN2_INPUT},        // AUDIO_SOURCE_YPbPr
    {AUDIO_NULL_INPUT},     // AUDIO_SOURCE_YPbPr2
    {AUDIO_AUIN2_INPUT},    // AUDIO_SOURCE_AV
    {AUDIO_NULL_INPUT},     // AUDIO_SOURCE_AV2
    {AUDIO_NULL_INPUT},     // AUDIO_SOURCE_AV3
    {AUDIO_NULL_INPUT},     // AUDIO_SOURCE_SV
    {AUDIO_NULL_INPUT},     // AUDIO_SOURCE_SV2
    {AUDIO_AUIN1_INPUT},    // AUDIO_SOURCE_SCART
    {AUDIO_NULL_INPUT},     // AUDIO_SOURCE_SCART2
    {AUDIO_HDMI_INPUT},    // AUDIO_SOURCE_HDMI
    {AUDIO_HDMI_INPUT},    // AUDIO_SOURCE_HDMI2
    {AUDIO_HDMI_INPUT},    // AUDIO_SOURCE_HDMI3
    {AUDIO_AUIN2_INPUT},    // AUDIO_SOURCE_DVI
    {AUDIO_AUIN2_INPUT},    // AUDIO_SOURCE_DVI2
    {AUDIO_AUIN2_INPUT},    // AUDIO_SOURCE_DVI3
    {AUDIO_AUMIC_INPUT}     // AUDIO_SOURCE_KTV
};



static AudioMux_t BOARD_AudioPath_t[BOARD_AUDIO_PATH_TYPE_SIZE] =
{
    {AUDIO_T3_PATH_AUOUT1},        // AUDIO_PATH_MAIN_SPEAKER
    {AUDIO_PATH_NULL}, 				// AUDIO_PATH_HP
    {AUDIO_T3_PATH_AUOUT0}, // AUDIO_PATH_LINEOUT
    {AUDIO_PATH_NULL}, // AUDIO_PATH_SIPOUT
    {AUDIO_T3_PATH_AUOUT0}, // AUDIO_PATH_SCART1
    {AUDIO_PATH_NULL}, // AUDIO_PATH_SCART2
    {AUDIO_T3_PATH_SPDIF},  // AUDIO_PATH_SPDIF
    {AUDIO_PATH_NULL},		    // AUDIO_PATH_HDMI
};


static AudioOutputType_t BOARD_AudioOutputType_t[BOARD_AUDIO_OUTPUT_TYPE_SIZE] =
{
    {AUDIO_HP_OUTPUT},     // AUDIO_OUTPUT_MAIN_SPEAKER
    {AUDIO_HP_OUTPUT},      // AUDIO_OUTPUT_HP
    {AUDIO_AUOUT0_OUTPUT},  // AUDIO_OUTPUT_LINEOUT
    {AUDIO_NULL_OUTPUT},  // AUDIO_OUTPUT_SIFOUT
    {AUDIO_AUOUT0_OUTPUT},  // AUDIO_OUTPUT_SCART1
    {AUDIO_NULL_OUTPUT},    // AUDIO_OUTPUT_SCART2
};


static AudioDefualtInit_t	BOARD_AudioDefaultInit_t =
{
	MAPI_AUDIO_SOURCE_DTV,		// Audio input source type
	MAPI_AUDIO_PATH_SIFOUT,     // Audio path type
	MAPI_AUDIO_OUTPUT_SIFOUT	// Audio output type

};

//**********************************************************************
//** Audio Amplifier
//**********************************************************************
#define DEFAULT_AUDIO_AMP   device_audio_amp_MSH9010


//**********************************************************************
//** DemuxInfo
//**********************************************************************

//With CI Card
static DemuxInfo_t DemuxInfo_With_IC_Card =
{
	//MAPI_DMX_INPUT   (u8DMX_Flow_input)
	DMX_FLOW_INPUT_EXT_INPUT0,
	//Clock phase inversion   (bClkInv)
	MAPI_FALSE,
	//Sync by extension signal    (bExtSync)
	MAPI_TRUE,
	//Parallel    (bParallel)
	MAPI_TRUE
};

//Without CI Card
static DemuxInfo_t DemuxInfo_WITHOUT_IC_CARD =
{
	//MAPI_DMX_INPUT   (u8DMX_Flow_input)
	DMX_FLOW_INPUT_DEMOD,
	//Clock phase inversion   (bClkInv)
    MAPI_TRUE,
	//Sync by extension signal    (bExtSync)
	MAPI_TRUE,
	//Parallel    (bParallel)
    MAPI_TRUE
};

DMXConf_t	BOARD_DMXConf_Table = {DemuxInfo_With_IC_Card,DemuxInfo_WITHOUT_IC_CARD};

//**********************************************************************
//** EDID Info
//**********************************************************************
#define BOARD_HDMI_EDID_InfoCount 4

